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HCS360 数据表(PDF) 10 Page - Microchip Technology |
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HCS360 数据表(HTML) 10 Page - Microchip Technology |
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10 / 28 page  HCSXXX DS41256A-page 10 Preliminary 2004 Microchip Technology Inc. TABLE 2-13: HCS412 18 X 16-BIT EEPROM MEMORY MAP 2.3 Entering Program Mode Entering the Program/Verify mode will be dependent upon the type of device in use. Most KEELOQ devices use a serial clock and bidirectional data line to access the chips' memory maps. In order to enter the Programming mode, a Start condition is sent to the target device, where the clock and data lines must be held high and low for specified periods of time. That is, all lines are held low while the clock line is driven high. After a short delay, the data line is driven high. At this point, both lines must remain high for another delay period prior to dropping back to ground. After dropping both lines low and providing another delay, the state machine for the KEELOQ device will enter the Programming mode and begin to wait for data, or depending on the component, a bulk erase is performed on the memory array. For the HCS360 and HCS361 devices, the Programming mode is entered by providing a clock source on the clock line and a Start pulse on the data line, as described in the previous paragraph. However, the difference is with driving the S1 pin, as shown in Figure 5-5. Bit 0 of the data packet must be driven on the S1 pin and kept at that level throughout the programming cycles and through verification. The HCS512 is another device that does not conform to the 2-wire protocol described above. For this device, the MCLR pin is driven high while data is held low. After the minimum setup time has been realized, the clock pin is driven high and then low for a minimum amount of time in order to send the HCS512 a Start condition and complete the Entry mode for the next programming sequence. The associated waveform is detailed in Section 5.0 “Program/Verify Mode Electrical Characteristics”. The HCS512 is also the only device that requires a checksum be sent to the target device while it is being programmed. See the Checksum Section in the HCS512 Data Sheet, “KEELOQ® Code Hopping Decoder“ (DS40151), for details on calculating the checksum. Word Address Mnemonic Description 0x00 KEY0 Word 0 (LSb’s) of 64-bit crypt key 1 0x01 KEY1 Word 1 of 64-bit crypt key 1 0x02 KEY2 Word 2 of 64-bit crypt key 1 0x03 KEY3 Word 3 (MSb’s) of 64-bit crypt key 1 0x04 SEED0 Word 0 (LSb’s) of 60-bit seed value 0x05 SEED1 Word 1 of 60-bit seed value 0x06 SEED2 Word 2 of 60-bit seed value 0x07 CFG/SEED3 Word 3 of 60-bit seed value/Configuration in top nibble 0x08 CONFIG1 Configuration Word 1 (security options) 0x09 CONFIG2 Configuration Word 2 0x0A SER0 Word 0 (LSb’s) of 32-bit serial number 0x0B SER1 Word 1 (MSb’s) of 32-bit serial number 0x0C USR0 Word 0 (LSb’s) of 64-bit user area 0x0D USR1 Word 1 of 64-bit user area 0x0E USR2 Word 2 of 64-bit user area 0x0F USR3 Word 3 (MSb’s) of 64-bit user area Note: The HCS512 requires an external clock signal for the OSCIN pin. This signal is necessary throughout the Programming mode. |
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