© Semiconductor Components Industries, LLC, 2001

February, 2001 – Rev.0

1

Publication Order Number:

AN8044/D

AND8044/D

Single-Channel 1206A

ChipFETt Power MOSFET

Recommended Pad Pattern

and Thermal Performance

INTRODUCTION

New ON Semiconductor ChipFETs in the leadless

1206A package feature the same outline as popular 1206A

resistors and capacitors but provide all the performance of

true power semiconductor devices. The 1206A ChipFET

has the same footprint as the body of the TSOP–6 and can

be thought of as a leadless TSOP–6 for purposes of

visualizing board area, but its thermal performance bears

comparison with the much large SO–8.

This

technical note discusses the single–channel

ChipFET 1206A pin–out, package outline, pad patterns,

evaluation board layout and thermal performance.

PIN–OUT

Figure 1 shows the pin–out description and Pin 1

identification for the single–channel 1206A ChipFET

device.

The

pin–out

is

similar

to

the

TSOP–6

configuration, with two additional drain pins to enhance

power dissipation and thermal performance. The legs of the

device are very short, again helping to reduce the thermal

path to the external heatsink/pcb and allowing a larger die

to be fitted in the device if necessary.

Figure 1. Single 1206A ChipFET

STYLE 1:

PIN 1. DRAIN

2. DRAIN

3. DRAIN

4. GATE

5. SOURCE

6. DRAIN

7. DRAIN

8. DRAIN

1

8

BASIC PAD PATTERNS

The basic pad layout with dimensions is shown in

Figure 2. This is sufficient for low power dissipation

MOSFET

applications,

but

power

semiconductor

performance requires a greater copper pad area, particularly

for the drain leads.

The minimum recommended pad pattern, shown in

Figure 3, improves the thermal area of the drain

connections (pins 1, 2, 3, 6, 7, 8) while remaining within the

confines of the basic footprint. The drain copper area is

0.0054 sq. in. or 3.51 sq. mm. This will assist the power

dissipation path away from the device (through the copper

leadframe) and into the board and exterior chassis (if

applicable) for the single device. The addition of a further

copper area and/or the addition of vias to other board layers

will enhance the performance still further. An example of

this method is implemented on the Evaluation Board

described in the next section (Figure 4).

Figure 2. Basic Pad Layout

Figure 3. Minimum Recommended Pad Pattern

1

2

3

4

8

7

6

5

1

2

3

4

8

7

6

5

26 mil

28 mil

80 mil

68 mil

28 mil

80 mil

25 mil

26 mil

18 mil

http://onsemi.com

APPLICATION NOTE