ADP1653

Rev. A | Page 17 of 24

APPLICATIONS INFORMATION

FLASH-CURRENT FOLDBACK DURING TRANSMIT

PULSE

The ADP1653 allows a fast, 1.8 V logic-enabled foldback of the

flash current, typically enabled shortly before an RF transmit

pulse. This feature extends the life of the battery by preventing

overstress of the battery cell. It also extends the life of the phone

by reducing the maximum instantaneous system current that

can occur, allowing a lower battery operating voltage limit.

2-Bit Logic Interface Mode (INTF = 1)

In 2-bit logic interface mode, the flash current is set with an

external resistor. The 1.22 V reference voltage is buffered to the

SETF pin, generating a reference current across an external SETF

resistor. This reference current is multiplied by a fixed gain to

set the flash current in the HPLED.

A 1.8 V compatible logic signal selects normal or reduced flash

current by adjusting the reference current, as shown in Figure 29

and Figure 30.

SETF

1.22V

1.22V

R1

R2

IREF

1.22V/R1

1.22V/R2

CURRENT

MIRRORS

DIGITAL

OUTPUT

TxMASK = 0V

Figure 29. Flash Mode Current Foldback

(Normal Operation with R2 Grounded Through Digital Control Signal)

Full-current flash mode has a reference current of

R2

R1

R2

R1

R2

R1

I

0

REF

×

+

×

=

=

)

(

V

22

.

1

//

V

22

.

1

_

(6)

The reference current is multiplied by a fixed gain to give the

actual flash current (see Table 8).

SETF

1.22V

1.22V

R1

R2

IREF

1.22V/R1

0.6V/R2

CURRENT

MIRRORS

DIGITAL

OUTPUT

TxMASK = 1.8V

1.8V

Figure 30. Flash Mode Current Foldback with 1.8 V Signal Applied to R2

A logic high to R2 changes the direction of the current in R2.

(7)

R2

V

R1

I

mask

Tx

REF

V

22

.

1

V

22

.

1

−

−

=

(8)

(9)

The ratio of full flash current to reduced flash current for

a 1.8 V logic signal is approximately

2

R1

R2

R1

R2

Flash

Reduced

Flash

Full

−

+

=

(10)

If R1 = R2 = 100 kΩ, maximum flash current is 500 mA, and

reduced flash current is 125 mA.

connect a resistor between SETF and ground, and another

resistor from SETF to the logic input, as shown in Figure 29 and

Figure 30. Operation is the same as for the 2-bit logic interface

mode, except the flash current is additionally scaled by setting

the HPLED bits in the OUT_SEL register.

Full-current flash mode (Tx mask = 0 V) has a flash current of

SETF

HPLED

R

Code

I

kΩ

50

mA)

15

mA

35

(

×

×

+

=

(11)

where:

Code is the HPLED register setting.

Bring the Tx mask voltage high for reduced reference current.

R2

V

R1

I

mask

Tx

REF

V

22

.

1

V

22

.

1

−

−

=

(12)

V

22

.

1

kΩ

50

mA)

15

mA

35

(

REF

HPLED

I

Code

I

×

×

×

+

=

(13)