17/41

STA323W

Table 12. DDX® Output Modes

7.4.2 5.3.2DDX® Variable Compensating Pulse Size

The DDX® variable compensating pulse size is intended to adapt to different power stage ICs. Contact

Apogee applications for support when deciding this function.

Table 13. DDX® Compensating Pulse

7.5 Configuration Register D (Address 03h)

7.5.1 High-Pass Filter Bypass

The STA323W features an internal digital high-pass filter for the purpose of DC Blocking. The purpose of

this filter is to prevent DC signals from passing through a DDX® amplifier. DC signals can cause speaker

damage.

7.5.2 De-Emphasis

By setting this bit to HIGH, or one (1), de-emphasis will implemented on all channels. DSPB (DSP Bypass,

Bit D2, CFA) bit must be set to 0 for De-emphasis to function.

OM (1,0)

Output Stage – Mode

00

Not Used

01

Not Used

10

DDX-2060/2100/2160

11

Variable Compensation

CSZ (4…0)

Compensating Pulse Size

00000

0 Clock period Compensating Pulse Size

00001

1 Clock period Compensating Pulse Size

……

10000

16 Clock period Compensating Pulse Size

……

11111

31 Clock period Compensating Pulse Size

D7

D6

D5

D4

D3

D2

D1

D0

MME

ZDE

DRC

BQL

PSL

DSPB

DEMP

HPB

00

0

0

0

0

0

0

BIT

R/W

RST

NAME

DESCRIPTION

0

R/W

0

HPB

High-Pass Filter Bypass Bit.

0 – AC Coupling High Pass Filter Enabled

1 – AC Coupling High Pass Filter Disabled

BIT

R/W

RST

NAME

DESCRIPTION

1

R/W

0

DEMP

De-emphasis:

0 – No De-emphasis

1 – De-emphasis