DA1017.002

29 May, 2002

5(6)

SAMPLES IN SBDIL 20 PACKAGE

NC

1

VDD 2

NC

3

DEC 4

AGC 5

NC

6

PUP 7

DCF 8

NC

9

NC

10

20 VSS

19 NC

18 RFI

17 PDN

16 NC

15 QO

14 NC

13 QI

12 NC

11 NC

PIN DESCRIPTION

Pin Name

Pin

Type

Function

Note

NC

1

VDD

2

P

Positive power supply

NC

3

DEC

4

AO

Demodulator capacitor

AGC

5

AO

AGC capacitor

NC

6

PUP

7

AI

Power up input

1

DCF

8

DO

Demodulator output

2

NC

9

NC

10

NC

11

NC

12

QI

13

AI

Quartz filter input

NC

14

3

QO

15

AO

Quartz filter output

NC

16

PDN

17

AI

Power down input

4

RFI

18

AI

Receiver input

NC

19

VSS

20

G

Power supply ground

Notes:

1) See power down control table on page 2.

-

Internal pull-down resistor > 1 M

Ω to VSS

2) DCF = VSS when carrier amplitude at maximum; DCF = VDD when carrier amplitude is reduced (25%

modulated)

-

-

at power down the output is high impedance

3) Pin 14 between quartz crystal filter pins must be connected to VSS to eliminate package leadframe parasitic

capacitances disturbing the crystal filter performance. All other NC (Not Connected) pins are also

recommended to be connected to VSS to minimize noise coupling.

4) See power down control logic table on page 2.

- Internal pull-up resistor > 1M

Ω to VDD