2 (10)

DA6179.000

22 January, 2007

PAD LAYOUT

QO2

QO1

QI

OUT

AGC

VSS

RFI2

RFIM

RFI3

PDN1

1420 µm

PDN2

DEC

QO3

RFIP

AON

MAS6179Ax,

x=1, 2

VDD

DIE size = 1.42 x 1.80 mm; rectangular PAD 80 µm x 80 µm

Note: Because the substrate of the die is internally connected to VSS, the die has to be connected to VSS or left

floating. Please make sure that VSS is the first pad to be bonded. Pick-and-place and all component assembly

are recommended to be performed in ESD protected area.

Note: Coordinates are pad center points where origin has been located in bottom-left corner of the silicon die.

Pad Identification

Name

X-coordinate

Y-coordinate

Note

Power Supply Voltage

VDD

154 µm

1580 µm

Quartz Filter Output for Crystal 2

QO2

154 µm

1393 µm

Quartz Filter Output for Crystal 1

QO1

154 µm

1207 µm

Quartz Filter Output for Crystal 3

QO3

154 µm

1021 µm

Quartz Filter Input for Crystals

QI

154 µm

835 µm

AGC Capacitor

AGC

154 µm

648 µm

Power Down/Frequency Selection Input 2

PDN2

154 µm

462 µm

1

Receiver Output

OUT

154 µm

276 µm

2

Demodulator Capacitor

DEC

1266 µm

276 µm

AGC On Control

AON

1266 µm

462 µm

3

Power Down/Frequency Selection Input 1

PDN1

1266 µm

648 µm

1

Receiver Input 3 (for Antenna Capacitor 3)

RFI3

1266 µm

835 µm

Positive Receiver Input

RFIP

1266 µm

1021 µm

4

Negative Receiver Input

RFIM

1266 µm

1207 µm

4

Receiver Input 2 (for Antenna Capacitor 2)

RFI2

1266 µm

1393 µm

Power Supply Ground

VSS

1266 µm

1580 µm

Notes:

1) PDN1 = PDN2 = VDD means receiver off

-

Fast start-up is triggered when the receiver is after power down controlled to power up

2) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced

(modulated)

-

-

at power down the output is pulled to VSS (pull down switch)

3) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working)

-

Internal pull-up with current < 1 µA which is switched off at power down

4) Receiver inputs RFIP and RFIM have both 600 kΩ biasing resistors towards VDD