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CSB1000JA 数据表(PDF) 52 Page - STMicroelectronics

部件名 CSB1000JA
功能描述  8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
PDF  153 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

CSB1000JA 数据表(HTML) 52 Page - STMicroelectronics

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14.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (MCC/RTC)
The Main Clock Controller consists of three differ-
ent functions:
s
a programmable CPU clock prescaler
s
a clock-out signal to supply external devices
s
a real time clock timer with interrupt capability
Each function can be used independently and si-
multaneously.
14.2.1 Programmable CPU clock prescaler
The programmable CPU clock prescaler supplies
the clock for the ST7 CPU and its internal periph-
erals. It manages SLOW power saving mode (See
Section 11.2 "SLOW MODE" on page 35 for more
details).
The prescaler selects the fCPU main clock frequen-
cy and is controlled by three bits in the MISCR1
register: CP[1:0] and SMS.
CAUTION: The prescaler does not act on the CAN
peripheral clock source. This peripheral is always
supplied by the fOSC/2 clock source.
14.2.2 Clock-out capability
The clock-out capability is an alternate function of
an I/O port pin that outputs a fOSC/2 clock to drive
external devices. It is controlled by the MCO bit in
the MISCR1 register.
CAUTION: When selected, the clock out pin sus-
pends the clock during ACTIVE-HALT mode.
14.2.3 Real time clock timer (RTC)
The counter of the real time clock timer allows an
interrupt to be generated based on an accurate
real time clock. Four different time bases depend-
ing directly on fOSC are available. The whole func-
tionality is controlled by four bits of the MCCSR
register: TB[1:0], OIE and OIF.
When the RTC interrupt is enabled (OIE bit set),
the ST7 enters ACTIVE-HALT mode when the
HALT instruction is executed. See Section 11.4
"ACTIVE-HALT AND HALT MODES" on page 37
for more details.
Figure 30. Main Clock Controller (MCC/RTC) Block Diagram
DIV 2, 4, 8, 16
MCC/RTC INTERRUPT
DIV 2
SMS
CP1 CP0
TB1 TB0
OIE
OIF
CPU CLOCK
MISCR1
RTC
COUNTER
TO CPU AND
PERIPHERALS
fOSC
fCPU
MCO
PORT
FUNCTION
ALTERNATE
MCO
-
-
-
-
0
0
0
0
MCCSR
fOSC/2



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