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CSTCS12.0MTA 数据表(PDF) 81 Page - STMicroelectronics |
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CSTCS12.0MTA 数据表(HTML) 81 Page - STMicroelectronics |
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81 / 153 page  ST72334J/N, ST72314J/N, ST72124J 81/153 SERIAL PERIPHERAL INTERFACE (Cont’d) 14.4.5 Low Power Modes 14.4.6 Interrupts Note: The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction). Mode Description WAIT No effect on SPI. SPI interrupt events cause the device to exit from WAIT mode. HALT SPI registers are frozen. In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with “exit from HALT mode” capability. Interrupt Event Event Flag Enable Control Bit Exit from Wait Exit from Halt SPI End of Transfer Event SPIF SPIE Yes No Master Mode Fault Event MODF Yes No |
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