TDA7535_06 datasheet(5/9 Pages) STMICROELECTRONICS

部件名	TDA7535

功能描述	DELTA/SIGMA CASCADE 20 BIT STEREO DAC

PDF	9 Pages

Scroll/Zoom	100%

制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

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TDA7535

Figure 2. I2S Timings

(1)

SCK clock defines the Fs, being the Sample Rate. This input clock needs a jitter below ~212psRMS

(2)

FSYNC switches inside the time window as specified w.r.t. to falling edge of SCK

Figure 3. Power Up & Reset Sequence

Timing

Description

Minimum

Maximum

Unit

tsck

Clock Cycle(1)

1/(64*Fs) -

150psRMS

1/(64*Fs) +

150psRMS

tsckpl

SCK Phase Low

0.5*tsck - 1%

0.5*tsck +1%

tsckph

SCK Phase High

0.5*tsck - 1%

0.5*tsck +1%

tlrw-

FSYNC switching time window before SCK falling edge(2)

0.125*tsck-10

tlrw+

FSYNC switching time window after SCK falling edge(2)

0.125*tsck-10

tsds

SDATA setup time

tsdh

SDATA hold time

tsckr

SCK rise time

tsckf

SCK fall time

tsck

tsckpl

tsds

tlrw-

tsckph

tlrw+

tsdh

Valid

FSYNC

SDATA

SCK

Valid

tsckf

tsckr

TRES

Min 50ms

VDD

RESET

D02AU1418

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