AD7952

Rev. 0 | Page 19 of 32

RD

CS

100nF

100nF

AVDD

10µF

100nF

10Ω

AGND

DGND

DVDD

OVDD

OGND

CNVST

BUSY

SDOUT

SDCLK

RESET

PD

REFBUFIN

D

CLOCK

AD7952

DIGITAL

INTERFACE

SUPPLY

(2.5V, 3.3V, OR 5V)

ANALOG

SUPPLY (5V)

OVDD

DIGITAL

SUPPLY (5V)

IN+

IN–

NOTE 5

ANALOG

INPUT+

2.7nF

U1

NOTE 1

OB/2C

REFGND

REF

PDBUF

PDREF

100nF

NOTE 3

NOTE 4

NOTE 3

NOTE 7

10µF

10µF

22µF

NOTES

1. ANALOG INPUTS ARE DIFFERENTIAL (ANTIPHASE). SEE ANALOG INPUTS SECTION.

2. THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION.

3. THE CONFIGURATION SHOWN IS USING THE INTERNAL REFERENCE. SEE VOLTAGE REFERENCE INPUT/OUTPUT SECTION.

4. A 22µF CERAMIC CAPACITOR (X5R, 1206 SIZE) IS RECOMMENDED (FOR EXAMPLE, PANASONIC ECJ4YB1A226M).

SEE VOLTAGE REFERENCE INPUT/OUTPUT SECTION.

5. OPTIONAL, SEE POWER SUPPLIES SECTION.

6. THE VCC AND VEE SUPPLIES SHOULD BE VCC = [VIN(MAX) + 2V] AND VEE = [VIN(MIN) – 2V] FOR BIPOLAR INPUT RANGES.

FOR UNIPOLAR INPUT RANGES, VEE CAN BE 0V. SEE POWER SUPPLIES SECTION.

7. OPTIONAL LOW JITTER CNVST, SEE CONVERSION CONTROL SECTION.

8. A SEPARATE ANALOG AND DIGITAL GROUND PLANE IS RECOMMENDED, CONNECTED TOGETHER DIRECTLY UNDER THE ADC.

SEE LAYOUT GUIDELINES SECTION.

ANALOG

INPUT–

NOTE 2

VCC

VEE

10µF

100nF

+7V TO +15.75V

SUPPLY

10µF

100nF

–7V TO –15.75V

SUPPLY

NOTE 6

HW/SW

SCCS

SCCLK

SCIN

BIPOLAR

TEN

SERIAL

PORT 1

SERIAL

PORT 2

WARP

IMPULSE

2.7nF

U1

NOTE 2

15Ω

15Ω

33Ω

AGND

DGND

NOTE 8

SER/PAR

MICROPROCESSOR/

DSP

Figure 27. Typical Connection Diagram Shown with Serial Interface and Serial Programmable Port