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UPD703003A 数据表(PDF) 21 Page - Renesas Technology Corp

部件名 UPD703003A
功能描述  MOS INTEGRATED CIRCUIT
PDF  45 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

UPD703003A 数据表(HTML) 21 Page - Renesas Technology Corp

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µPD703003A, 703004A, 703025A, 703003A(A), 703025A(A)
Data Sheet U13188EJ6V1DS
Data Retention Characteristics (TA = –40 to +85
°C, VDD = VDDDR)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Data retention voltage
VDDDR
STOP mode
1.5
5.5
V
Data retention current
IDDDR
Note 1
0.4VDDDR
50
µA
Note 2
0.4VDDDR
200
µA
Power supply voltage rise time
tRVD
200
µs
Power supply voltage fall time
tFVD
200
µs
Power supply voltage hold time
tHVD
0ms
(vs. STOP mode setting)
STOP mode release signal input time tDREL
Note 3
0ns
Data retention high-level input voltage
VIHDR
Note 3
0.9VDDDR
VDDDR
V
Data retention low-level input voltage
VILDR
0
0.1VDDDR
V
Notes 1. –40
°C ≤ TA ≤ +50°C
2. 50
°C <TA ≤ 85°C
3. P02 to P07, P12 to P17, P23, P24, P26, P27, P32 to P37, P112 to P117, RESET, NMI, MODE, X1, and
their alternate-function pins.
Remark
TYP. values are reference values for when TA = 25
°C (except for the conditions in Note 2) and VDD =
5.0 V.
tHVD
VDD
VDD
tFVD
tRVD
tDREL
VDD
VDDDR
RESET (input)
VIHDR
NMI (input)
(Released at falling edge)
VIHDR
VILDR
NMI (input)
(Released at rising edge)
STOP mode setting (fifth clock after PSC register is set)



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