RT4841

13

DS4841-00 May 2021

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2021 Richtek Technology Corporation. All rights reserved.

is a registered trademark of Richtek Technology Corporation.

Input Capacitor Selection

For the power stage, because of the inductor current ripple,

the input voltage changes if there is parasite inductance

and resistance between the power supply and the inductor.

It is recommended to have enough input capacitance to

make smaller the input voltage ripple. Generally, three

10

μF input capacitances are sufficient for most

applications.

The value of the input capacitance CIN of a boost converter

is generally selected to limit the input voltage ripple

ΔVIN

specified by the application. For CCM mode operation,

the current flowing through CIN is primarily determined

by the inductor ripple current

ΔIL.

The DVIN can be calculated as the following equation :

LSW

IN

IN

IT

C

8V







Where

ΔIL is the inductor ripple current and TSW is s

witching period. Low ESR ceramic capacitors are

recommended for input capacitor applications. Low ESR

will effectively reduce the input voltage ripple. The

ΔVESR

can be calculated as the following equation :

ΔVESR = ESR x ΔIL

Another consideration is the voltage rating of the input

capacitor which must be greater than the maximum input

voltage.

Loop Compensation

The external compensation network of the RT4841 must

be compensated by the designer to ensure the stability

of the overall loop response. In power-supply design, a

power supply is typically defined to be stable if the gain

margin is greater than 10dB and the phase margin is

greater than 45°. The requirement for stability is typically

forcing the loop to cross over with a -1 slope, or -20dB/

Decade in the vicinity of the crossover frequency.

A relationship exists between the phase margin of a

second-order closed-loop system and the quality

coefficient Q of its transfer function. If the phase margin is

too small, the peaking induces high output ringing, exactly

as in an RLC circuit. On the contrary, if the phase margin

becomes too large, it slows down the system : the

overshoot goes away but to the detriment of response

and recovery speed.

The stability exercise requires shaping the compensation

circuit G(s) in order to provide adequate phase margin at

the selected crossover point, together with a high gain in

dc. Choose R4 to set high frequency integrator gain for

fast transient response and C9 to set the integrator zero

to maintain loop stability.

For typical application, VIN = 12V, SWO = 14.5V, C6 =

10

μF x 6, L1 = 10μH, while the recommended value for

compensation is as follows : R4 = 33k

Ω, C9 = 1nF.

Thermal Considerations

The junction temperature should never exceed the

absolute maximum junction temperature TJ(MAX), listed

under Absolute Maximum Ratings, to avoid permanent

damage to the device. The maximum allowable power

dissipation depends on the thermal resistance of the IC

package, the PCB layout, the rate of surrounding airflow,

and the difference between the junction and ambient

temperatures. The maximum power dissipation can be

calculated using the following formula :

PD(MAX) = (TJ(MAX)

− TA) / θJA

where TJ(MAX) is the maximum junction temperature, TAis

the ambient temperature, and

θJA is the junction-to-ambient

thermal resistance.

For continuous operation, the maximum operating junction

temperature indicated under Recommended Operating

Conditions is 125

°C. The junction-to-ambient thermal

resistance,

θJA, is highly package dependent. For a

WQFN-20L 4x4, the thermal resistance,

θJA, is 28°C/W

on a standard JEDEC 51-7 high effective-thermal-

conductivity four-layer test board. The maximum power

dissipation at TA = 25

°C can be calculated as below :

PD(MAX) = (125

°C − 25°C) / (28°C/W) = 3.57W for a

WQFN-20L 4x4 package.

The maximum power dissipation depends on the operating

ambient temperature for the fixed TJ(MAX) and the thermal

resistance,

θJA. The derating curves in Figure 2 allows

the designer to see the effect of rising ambient temperature

on the maximum power dissipation.