| 数据搜索系统,热门电子元器件搜索 |
|
SP809 数据表(PDF) 5 Page - Sipex Corporation |
|
|
|||||||||||||||||||||||||||||
SP809 数据表(HTML) 5 Page - Sipex Corporation |
|
5 / 8 page ![]() 5 Date: 5/02/06 Rev B SP809/810, 3 Pin Microprocessor Supervisor Circuit © Copyright 2006 Sipex Corporation PIN DESCRIPTION e m a N n i P n o i t p i r c s e D D N G . d n u o r G ) 9 0 8 P S ( T E S E R t e s e r e h t w o l e b s i C C V e li h w w o l s n i a m e r t u p t u O T E S E R . n i p t u p t u o w o l e v i t c A . d l o h s e r h t ) 0 1 8 P S ( T E S E R t e s e r e h t w o l e b s i C C V e li h w h g i h s n i a m e r t u p t u O T E S E R . n i p t u p t u o h g i h e v i t c A . d l o h s e r h t V C C e g a t l o V y l p p u S µP will be activated at a valid reset state. These µP supervisory circuits assert reset to prevent code execution errors during power- up, power-down, or brownout conditions. Reset is guaranteed to be a logic low for V TH>VCC>0.9V. Once VCC exceeded the reset threshold, an internal timer keeps RESET low for the reset timeout period; after this interval, RESET goes high. If a brownout condition occurs (V CC drops below the reset threshold), RESET goes low. Any time V CC goes below the reset threshold, the internal timer resets to zero, and RESET goes low. The internal timer is activated after V CC returns above the reset threshold, and RESET remains low for the reset timeout period. DETAILED DESCRIPTION Benefits of Highly Accurate Reset Threshold SP809/810 with specified voltage as 5V±10% or 3V±10% are ideal for systems using a 5V±5% or 3V±5% power supply. The reset is guaranteed to assert after the power supply falls below the minimum specified operating voltage range of the system ICs. The pretrimmed thresholds are reducing the range over which an undesirable reset may occur. APPLICATION INFORMATION Negative-Going V CC Transients In addition to issuing a reset to the µP during power-up, power-down, and brownout condi- tions, SP809 series are relatively resistant to short-duration negative-going V CC transient. Ensuring a Valid Reset Output Down to VCC= 0 When V CC falls below 0.9V, SP809 RESET output no longer sinks current; it becomes an open circuit. In this case, high-imped- ance CMOS logic inputs connecting to RESET can drift to undetermined voltages. Therefore, SP809/810 with CMOS is perfect for most applications of V CC down to 0.9V. However in applications where RESET must be valid down to 0V, adding a pull- down resistor to RESET causes any leakage currents to flow to ground, holding RESET low. Interfacing to µP with Bidirectional Reset Pins The RESET output on the SP809N is open drain, this device interfaces easily with µPs that have bidirectional reset pins. Connect- ing the µP supervisor's RESET output directly to the microcontroller's RESET pin with a single pull-up resistor allows either device to assert reset. |
|
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |