SN54ACT74, SN74ACT74

DUAL POSITIVEEDGETRIGGERED DTYPE FLIPFLOPS

WITH CLEAR AND PRESET

SCAS520H − AUGUST 1995 − REVISED OCTOBER 2003

2

POST OFFICE BOX 655303

FUNCTION TABLE

(each flip-flop)

INPUTS

OUTPUTS

PRE

CLR

CLK

D

Q

Q

L

H

X

X

H

L

H

LX

XL

H

L

LX

X

H†

H†

H

H

↑

HH

L

H

H

↑

LL

H

H

H

L

X

Q0

Q0

† This configuration is nonstable; that is, it does not

persist when either PRE or CLR returns to its

inactive (high) level.

logic diagram, each flip-flop (positive logic)

C

C

C

C

C

C

C

C

TG

TG

TG

TG

Q

Q

PRE

CLK

D

CLR

C

C