WM8721 / WM8721L

Production Data

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PD Rev 4.0 November 2004

28

REGISTER MAP

The complete register map is shown in Table 21. The detailed description can be found in the

relevant text of the device description. There are 9 registers with 9 bits per register. These can be

controlled using either the 2 wire or 3 wire MPU interface.

REGISTER

B

15

B

14

B

13

B

12

B

11

B

10

B

9

B8

B7

B6

B5

B4

B3

B2

B1

B0

R2 (04h)

0

0

0

0

0

1

0

LRHP

BOTH

LZCEN

LHPVOL

R3 (06h)

0

0

0

0

0

1

1

RLHP

BOTH

RZCEN

RHPVOL

R4 (08h)

0

0

0

0

1

0

0

0

0

0

0

DAC SEL

0

0

0

0

R5 (0Ah)

0

0

0

0

1

0

1

0

0

0

0

0

DAC MU

DEEMPH

0

R6 (0Ch)

0

0

0

0

1

1

0

0

POWER

OFF

1

1

OUTPD

DACPD

1

1

1

R7 (0Eh)

0

0

0

0

1

1

1

0

BCLK

INV

MS

LR SWAP

LRP

IWL

FORMAT

R8 (10h)

0

0

0

1

0

0

0

0

0

CLKI

DIV2

SR

BOSR

USB/ NORM

R9 (12h)

0

0

0

1

0

0

1

0

0

0

0

0

0

0

0

ACTIVE

R15(1Eh)

0

0

0

1

1

1

1

RESET

ADDRESS

DATA

Table 19 Mapping of Program Registers

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

6:0

LHPVOL

[6:0]

1111001

( 0dB )

Left Channel Headphone Output

Volume Control

1111111 = +6dB

. . 1dB steps down to

0110000 = -73dB

0000000 to 0101111 = MUTE

7

LZCEN

0

Left Channel Zero Cross detect

Enable

1 = Enable

0 = Disable

0000010

Left Headphone

Out

8

LRHPBOTH

0

Left to Right Channel Headphone

Volume, Mute and Zero Cross Data

Load Control

1 = Enable Simultaneous Load of

LHPVOL[6:0] and LZCEN to

RHPVOL[6:0] and RZCEN

0 = Disable Simultaneous Load