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TSM111 数据表(PDF) 13 Page - STMicroelectronics

部件名 TSM111
功能描述  TRIPLE VOLTAGE AND CURRENT SUPERVISOR
PDF  17 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

TSM111 数据表(HTML) 13 Page - STMicroelectronics

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TSM111
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EVALUATION BOARD - TECHNICAL NOTE
TSM111 is a Housekeeping IC which is best used
in PC Switch Mode Power Supplies for secondary
3.3V, 5V, and 12V power lines protection.
TSM111 integrates all the necessary functions for
a secure and reliable overcurrent and overvoltage
protection, as well as a logic interface for proper
communication with the motherboard and adjust-
able timing circuitry for optimized sequencing
management. Moreover, TSM111 integrates two
precise shunt voltage references for direct opto-
coupler drive. TSM111, integrating the equivalent
of more than 25 discrete components, saves a lot
of design time and fine tuning, as well as PCB ar-
ea, and increases the reliability of the whole appli-
cation.
How to use the TSM111 Evaluation Board ?
This evaluation board allows to adapt the TSM111
housekeeping chip to an already existing PC Pow-
er Supply by simply choosing proper values for it’s
external components, and making the adequate
connections to the I/O of the evaluation board.
The Electrical Schematic of the TSM111 evalua-
tion board is shown on figure 1. It includes the
TSM111 as well as the minimum component num-
ber required to make the TSM111 fit in a PC
SMPS application.
Components calculations
The overvoltage protection is not to be adjusted.
Internal voltage thresholds are given by Vvs1,
Vvs2, Vvs3 for respective protection of the 3.3V,
5V, 12V power lines.
The overcurrent protection is given by the choice
of the Sense resistors R1, R2, R3 (respectively for
each power line 3.3V, 5V, 12V). Internal precise
voltage thresholds define the tripping voltage
drops for each line following equations 1, 2 & 3 :
Vcs1 = R1 x I33
eq1
Vcs2 = R2 x I5
eq2
Vcs3 = R3 x I12
eq3
where I33, I5, and I12 are the tripping currents.
The system will latch (Fault output will be active -
high) if the overcurrent lasts more than the autho-
rized surge delay Tsur given by equations 4 & 5 :
Icharge = Vcc / R4
eq4
Tsur = (C1 x Vsur) / Icharge
eq5
Note that eq4 is an approximation of a capacitive
charge where Vcc (16V min) is large versus the
threshold voltage Vsur (2.5V).
R4=33k
Ω, C1=4.7µF => Tsur=21ms
Thanks to the Tsur adjustment, the normal surge
currents which occur during power up (capacitive
oads charging) are blanked for a time depending
on each application.
PG
9
Tpor
10
Rem
7
UV
11
Tsur
17
PWM
6
U1
TSM111
R1
rs3.3V
R2
rs5V
R3
rs12V
D1
UV
R4
Rsur
C1
Csur
C2
Crem
R5 R rem
C3
Cpor
R6
1
2
J1
Vdet
1
2
J2
Fault
1
2
J3
Optaux
1
J5
In3.3V
1
J6
1
J7
In3.3V
Vdet
Optaux
Fault
In5V
In12V
Out12V
Out5V
Out3.3V
1
J8
Out12V
1
J9
Out5V
1
J10
Out3.3V
PG
1
2
J11
PG
1
2
3
4
SW1
BP Rem
1
2
J12
Rem
From µc
5Vstby
5Vstby
1
2
J13
Vcc
1
2
J14
Gnd
VCC
1
2
J15
VrefMain
VrefMain
R7
RoptMain
VrefAux
R8
R9
Roptaux
C4
C5
1
2
J16
VrefAux
R10
1
2
J20
D5
D6
I
1INV
1
2
J18
OptMain
OptMain
Vin
2
Vout
3
U2 78L05
5Vstby
+
C7
R11
5Vstby
In5V
IN12V
EVALUATION BOARD - ELECTRICAL SCHEMATIC
C6



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