CS5155

http://onsemi.com

14

Figure 21. Input Filter

1200 pF × 3.0/16 V

2.0 μH

+

Layout Guidelines

1. Place 12 V filter capacitor next to the IC and connect

capacitor ground to pin 11 (PGND).

2. Connect pin 11 (PGND) with a separate trace to the

ground terminals of the 5.0 V input capacitors.

and connect it’s ground terminal with a separate, wide

trace directly to pin 14 (LGND).

4. Connect the ground terminals of the Compensation

capacitor directly to the ground of the fast feedback

filter capacitor to prevent common mode noise from

effecting the PWM comparator.

5. Place the output filter capacitor(s) as close to the load

as possible and connect the ground terminal to pin 14

(LGND).

6. To implement adaptive voltage positioning, connect

terminal. Connect inductor to the output capacitors via

a trace with the following resistance:

RTRACE + 80 mV

IMAX

This causes the output voltage to be +40 mV with no

load, and −40 mV with a full load, improving regulator

transient response. This trace must be wide enough to

carry the full output current. (Typical trace is 1.0 inch

long, 0.17 inch wide). Care should be taken to

minimize any additional losses after the feedback

connection point to maximize regulation.

7. If DC regulation is to be optimized (at the expense of

degraded transient regulation), adaptive voltage

directly to the load with a separate trace (remote

sense).

8. Place 5.0 V input capacitors close to the switching

MOSFET and synchronous MOSFET.

minimum of 0.025 inches wide.

Figure 22. Layout Guidelines

To the negative terminal of the output capacitors

100 pF

0.1 μF

SOFT START

OFF TIME

To the negative terminal

of the input capacitors

15

11

5

8

1.0 μF