IP5568

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7. PCB Layout

Here below lists essential precautions that may affect the function and performance on PCB layout, more

details will be attached in another document if any.

Location of VSYS capacitor

The power and current of the chip are relatively large, and the position of the capacitor on the vsys network

will affect the stability of the DCDC. The capacitors on the vsys network need to be as close to the vsys pin and

EPAD of the IC as possible, and copper is laid on a large area, and more vias are added to reduce the area of

current loop between the capacitors and the IC and reduce parasitic parameters.

Vsys pins are distributed on both sides of the chip, and capacitors need to be placed near the pins on both

sides, and the vsys pins on both sides are connected by a wide (no less than 100mil) copper laying on the PCB