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M95640-R 数据表(PDF) 12 Page - STMicroelectronics

部件名 M95640-R
功能描述  32 Kbit and 64 Kbit Serial SPI bus EEPROMs with high speed clock
PDF  44 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

M95640-R 数据表(HTML) 12 Page - STMicroelectronics

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Operating features
M95320, M95640, M95320-x, M95640-x
12/44
4.1.4
Power-down
At Power-down (continuous decrease of VCC), as soon as VCC drops from the normal
operating voltage to below the Power On Reset threshold voltage, the device stops
responding to any instruction sent to it.
During Power-down, the device must be deselected and in Standby Power mode (that is
there should be no internal Write cycle in progress). Chip Select (S) should be allowed to
follow the voltage applied on VCC.
4.2
Active Power and Standby Power modes
When Chip Select (S) is Low, the device is selected, and in the Active Power mode. The
device consumes ICC, as specified in Table 13 to Table 17.
When Chip Select (S) is High, the device is deselected. If an Erase/Write cycle is not
currently in progress, the device then goes in to the Standby Power mode, and the device
consumption drops to ICC1.
4.2.1
Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To enter the Hold condition, the device must be selected, with Chip Select (S) Low.
Normally, the device is kept selected, for the whole duration of the Hold condition.
Deselecting the device while it is in the Hold condition, has the effect of resetting the state of
the device, and this mechanism can be used if it is required to reset any processes that had
been in progress.
The Hold condition starts when the Hold (HOLD) signal is driven Low at the same time as
Serial Clock (C) already being Low (as shown in Figure 5).
The Hold condition ends when the Hold (HOLD) signal is driven High at the same time as
Serial Clock (C) already being Low.
Figure 5 also shows what happens if the rising and falling edges are not timed to coincide
with Serial Clock (C) being Low.
Figure 5.
Hold condition activation
AI02029D
HOLD
C
Hold
Condition
Hold
Condition



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