M41T94

Operation

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3.1

SPI bus characteristics

The Serial Peripheral interface (SPI) bus is intended for synchronous communication between different

ICs. It consists of four signal lines: Serial data input (SDI), Serial data output (SDO), Serial clock (SCL)

and a Chip Enable (E).

By definition a device that gives out a message is called “transmitter,” the receiving device that gets the

message is called “receiver.” The device that controls the message is called “master.” The devices that

are controlled by the master are called “slaves.”

The E input is used to initiate and terminate a data transfer. The SCL input is used to synchronize data

transfer between the master (micro) and the slave (M41T94) devices.

The SCL input, which is generated by the microcontroller, is active only during address and data transfer

to any device on the SPI bus (see Figure 5 on page 9).

The M41T94 can be driven by a microcontroller with its SPI peripheral running in either of the two

following modes:

●

(CPOL, CPHA) = ('0', '0') or

●

(CPOL, CPHA) = ('1', '1').

For these two modes, input data (SDI) is latched in by the low-to-high transition of clock SCL, and output

data (SDO) is shifted out on the high-to-low transition of SCL (see Table2 on page10 and Figure 6 on

page 10).

There is one clock for each bit transferred. Address and data bits are transferred in groups of eight bits.

Due to memory size the second most significant address bit is a Don’t Care (address bit 6).

Figure 7.

Input timing requirements

AI04633

SCL

SDI

E

MSB IN

SDO

tDVCH

HIGH IMPEDANCE

LSB IN

tELCH

tCHDX

tDLDH

tDHDL

tCHCL

tCLCH

tEHCH

tEHEL

tCHEH