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ES9033 数据表(PDF) 65 Page - ESS Technology,Inc |
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ES9033 数据表(HTML) 65 Page - ESS Technology,Inc |
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65 / 103 page  0.3.1 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 ES9033 Datasheet Information 65 Register 40: TDM CONFIG3 Bits [7] [6:5] [4:0] Default 1’d0 2’d0 5’d0 Bits Mnemonic Description [7] PDM_NEG_FIRST PDM data edge polarity control. • 2’b0: PDM data ch1/2 are on positive/negative edges of PDM clock (default) • 2’b1: PDM data ch1/2 are on negative/positive edges of PDM clock [6:5] TDM_BIT_WIDTH Bit width of each TDM slot. • 2’b00: 32-bit (default) • 2’b01: 24-bit • 2’b10: 16-bit • 2’b11: Reserved [4:0] TDM_DATA_LATCH_ADJ Sets the position of the start bit within each TDM slot Can be moved +ve or -ve relative to MSB. • 5’d00: Default • 5’d16: Start bit shifted 16 bits towards LSB • 5’d31: Start bit shifted 16 bits towards MSB Register 41: RESERVED Register 42: TDM SLOT CONFIG Bits [7:4] [3:0] Default 4’d1 4’d0 Bits Mnemonic Description [7:4] TDM_CH2_SLOT_SEL CH2 data slot selection. CH2 receives data from Mth slot. M = TDM_CH2_SLOT_SEL + 1. • 4’d00: Minimum (M=1) • 4’d15: Maximum (M=16) [3:0] TDM_CH1_SLOT_SEL CH1 data slot selection. CH1 receives data from Mth slot. M = TDM_CH1_SLOT_SEL + 1. • 4’d00: Minimum (M=1) • 4’d15: Maximum (M=16) Register 43: RESERVED |
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