SN74S1053

16-BIT SCHOTTKY BARRIER DIODE

BUS-TERMINATION ARRAY

SDLS017A – SEPTEMBER 1990 – REVISED AUGUST 1997

1

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

D Designed to Reduce Reflection Noise

D Repetitive Peak Forward Current to 200 mA

D 16-Bit Array Structure Suited for

Bus-Oriented Systems

D Package Options Include Plastic

Small-Outline Packages and Standard

Plastic 300-mil DIPs

description

This Schottky barrier diode bus-termination array

is designed to reduce reflection noise on memory

bus lines. This device consists of a 16-bit

high-speed Schottky diode array suitable for

clamping to VCC and/or GND.

The SN74S1053 is characterized for operation

from 0

°C to 70°C.

schematic diagrams

D01

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D02

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D03

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D04

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D05

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D06

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D07

8

D08

9

D09

12

D10

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D11

14

D12

15

D13

16

D14

17

D15

18

D16

19

10

GND

11

GND

VCC

1

VCC

20

Copyright

© 1997, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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2

3

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10

20

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11

VCC

D01

D02

D03

D04

D05

D06

D07

D08

GND

VCC

D16

D15

D14

D13

D12

D11

D10

D09

GND

DW OR N PACKAGE

(TOP VIEW)