M41T80

Clock operation

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3

Clock operation

The M41T80 is driven by a quartz-controlled oscillator with a nominal frequency of

32,768Hz. The accuracy of the Real Time Clock depends on the frequency of the quartz

crystal that is used as the time-base for the RTC.

The 20-byte Register Map (see Table 3: Clock register map on page 14) is used to both set

the clock and to read the date and time from the clock, in a binary coded decimal format.

Tenths/Hundredths of Seconds Minutes, and Hours are contained within the first four

registers.

Note:

A WRITE to any clock register will result in the Tenths/Hundredths of Seconds being reset to

“00,” and Tenths/Hundredths of Seconds cannot be written to any value other than “00.”

Bits D6 and D7 of Clock Register 03h (Century/Hours Register) contain the CENTURY

ENABLE Bit (CEB) and the CENTURY Bit (CB). Setting CEB to a '1' will cause CB to toggle,

either from '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial

state). If CEB is set to a '0,' CB will not toggle. Bits D0 through D2 of Register 04h contain

the Day (day of week). Registers 05h, 06h, and 07h contain the Date (day of month), Month

and Years. The ninth clock register is the Control Register. Bit D7 of Register 01h contains

the STOP Bit (ST). Setting this bit to a '1' will cause the oscillator to stop. If the device is

expected to spend a significant amount of time on the shelf, the oscillator may be stopped to

reduce current drain. When reset to a '0' the oscillator restarts within four seconds (typically

one second).

The eight Clock Registers may be read one byte at a time, or in a sequential block. Provision

has been made to assure that a clock update does not occur while any of the eight clock

addresses are being read. If a clock address is being read, an update of the clock registers

will be halted. This will prevent a transition of data during the READ.

3.1

Clock registers

The M41T80 offers 20 internal registers which contain Clock, Alarm, 32kHz, Flag, Square

Wave, and Control data. These registers are memory locations which contain external (user

external copies are independent of internal functions except that they are updated

periodically by the simultaneous transfer of the incremented internal copy. The internal

divider (or clock) chain will be reset upon the completion of a WRITE to any clock address.

The system-to-user transfer of clock data will be halted whenever the address being read is

a clock address (00h to 07h). The update will resume either due to a Stop Condition or when

the pointer increments to any non-clock address (08h-13h).

Clock and Alarm Registers store data in BCD. Control, 32kHz, and Square Wave Registers

store data in Binary Format.