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M65KA128AL 数据表(PDF) 27 Page - STMicroelectronics

部件名 M65KA128AL
功能描述  128Mbit (4 Banks x 2M x 16) 1.8V Supply, Low Power SDRAMs
PDF  53 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

M65KA128AL 数据表(HTML) 27 Page - STMicroelectronics

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M65KA128AL
DC and AC parameters
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Table 14.
Asynchronous AC Characteristics
Symbol
Parameter
M65KA128AL
Unit(1)
Min
Max
tDPL
Data Input Valid to Precharge Command
2
tCK
tDAL
Data Input Valid to Bank/Row Activate
Command
CAS Latency = 3
2CLK + 28.5
ns
CAS Latency = 2
2CLK + 30
ns
tDQZ
UDQM or LDQM High to Data Output Hi-Z
2
tCK
tDQM
UDQM or LDQM High to Data Input Masked
0
tCK
tMRD
Mode Register Set Cycle Time
2
tCK
tRC
RAS Cycle Time
86
ns
tRCD
Delay Time, RAS Active to CAS Active
28.5
ns
tRAS
RAS Active Time
57
120,000
ns
tRP
RAS Precharge Time
28.5
ns
tRRD
Delay Time, RAS Active to RAS Bank Active
2
tCK
tRC1
Auto Refresh Exit Time
105
ns
tRC2
(2)
Self Refresh Exit Time
105
ns
tREF
Refresh Time
64
ms
tτ
Transition Time
1
30
ns
tWTL
Delay Time, Write Command to Data Input
0
tCK
1.
The unit tCK is the system Clock cycle time.
2.
A new command can be issued tRC after the Self Refresh mode is exited.



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