April 2004

5

M9999-042204

MIC2593

Micrel

Pin Description (cont)

Pin Number

Pin Name

Pin Function

13

3VSENSEA

3V Circuit Breaker Sense Input [A/B]: The current limit thresholds are set by

24

3VSENSEB

connecting sense resistors between these pins and 3VIN[A/B]. When the

current limit threshold of IR = 50mV is reached, the 3VGATE[A/B] pin is

modulated to maintain a constant voltage across the sense resistor and

therefore a constant current into the load. If the 50mV threshold is exceeded

for t

and the GATE pin for the affected supply’s external MOSFET is immediately

pulled low.

16

3VOUTA

3.3V Power-Good Sense Inputs: Connect to 3.3V[A/B] outputs. Used to

21

3VOUTB

monitor the 3.3V output voltages for Power-is-Good status.

14

3VGATEA

3V Gate Drive Output [A/B]: Each pin connects to the gate of an external

23

3VGATEB

N-channel MOSFET. During power-up, the C

MOSFETs are connected to a 25

µA current source. This controls the value

of dv/dt seen at the source of the MOSFETs, and hence the current flowing

into the load capacitance.

During current limit events, the voltage at this pin is adjusted to maintain

constant current through the switch for a period of t

overcurrent, thermal shutdown, or input undervoltage fault condition occurs,

the GATE pin for the affected slot is immediately brought low. During power

down, these pins are discharged by an internal current source.

11

VSTBYA

3.3V Standby Input Voltage: Required to support PCI VAUX output.

26

VSTBYB

Additionally, the SMBus logic and internal registers run off of VSTBY[A/B]

to ensure that the MIC2593 is accessible during standby modes. A UVLO

circuit prevents turn-on of this supply until VSTBY[A/B] rises above its UVLO

threshold. Both pins must be connected together externally at the IC.

15

VAUXA

3.3VAUX[A/B] Output to PCI Card Slot: These outputs connect

22

VAUXB

the 3.3AUX pin of the PCI connectors to VSTBY[A/B] via internal

400m

Ω MOSFETs. These outputs are current limited and protected against

short-circuit faults.

44

ONA

Enable Inputs: Rising-edge triggered. Used to enable or disable the MAINA

43

ONB

and MAINB (5V, 3.3V, +12V and –12V) outputs. Taking ON[A/B] low after a

fault resets the 5V, 3.3V, +12V and/or –12V fault latches for the affected slot.

Tie these pins to GND if using SMI power control. Also, see pin description

for /FAULTA and /FAULTB.

45

AUXENA

Enable Inputs: Rising-edge triggered. Used to enable or disable VAUXA and

42

AUXENB

VAUXB outputs. Taking AUXEN[A/B] low after a fault resets the respective

slot’s Aux Output Fault Latch. Tie these pins to GND if using SMI power

control. Also, see pin description for /FAULTA and /FAULTB.

2

CFILTERA

Overcurrent Timer (Filter) Capacitor [A/B]: Capacitors connected between

35

CFILTERB

these pins and GND set the duration of t

which a slot remains in current limit before its circuit breaker is tripped.

1

/FAULTA

/FAULT[A/B] Outputs: Open-drain, active-low. Asserted whenever the

36

/FAULTB

circuit breaker trips due to a fault condition (overcurrent, input undervoltage,

overtemperature). Each pin requires an external pull-up resistor to VSTBY.

Bringing the slot’s ON[A/B] pin low resets /FAULT[A/B] if /FAULT[A/B]

was asserted in response to a fault condition on one of the slot’s MAIN

outputs (5V, 3.3V, +12V, or –12V).

/FAULT[A/B] is reset by bringing the slot’s AUXEN[A/B] pin low if

/FAULT[A/B] was asserted in response to a fault condition on the slot’s V

AUX

output. If a fault condition occurred on both the MAIN and VAUX[A/B]

outputs of the same slot, then both ON[A/B] and AUXEN[A/B] must be

brought low to de-assert the /FAULT[A/B] output.