5

TYPE III LOOP COMPENSATION DESIGN

The open loop gain of the SP7650EB can be divided into the gain of the error amplifier

Gamp(s), PWM modulator Gpwm, buck converter output stage Gout(s), and feedback

resistor divider Gfbk. In order to crossover at the selecting frequency fco, the gain of

the error amplifier has to compensate for the attenuation caused by the rest of the loop

at this frequency. The goal of loop compensation is to manipulate the open loop

frequency response such that its gain crosses over 0dB at a slope of –20dB/dec. The

open loop crossover frequency should be higher than the ESR zero of the output

capacitors but less than 1/5 to 1/10 of the switching frequency fs to insure proper

operation. Since the SP7650EB is designed with Ceramic Type output capacitors, a

Type III compensation circuit is required to give a phase boost of 180

° in order to

counteract the effects of the output LC under damped resonance double pole

frequency.

(SRz2Cz2+1)(SR1Cz3+1)

SR1Cz2(SRz3Cz3+1)(SRz2Cp1+1)

Vin

Vramp_pp

(SResrCout+1)

[S^2LCout+S(Resr+Rdc)Cout+1]

(R1+R2)

R2

OR

Vout

Vref

Vout

(Volts)

Vref

(Volts)

Type III Voltage Loop

(Volts)

Vfbk

Gout(S)

Gain Block

Compensation Gamp(S)

PWM Stage

Output Stage

Gain Block

Gain Block

Gpwm

Gain Block

Gfbk

Voltage Feedback

Resr

:= Output Capacitor Equivalent Series Resitance

Definitions:

Rdc

:= Output Inductor DC Resistance

Vramp_pp := SP7650 Internal RAMP Amplitude Peak to Peak Voltage

Output Load Resistance >> Resr and Rdc

Cz2 >> Cp1 and R1 >> Rz3

Conditions:

Figure 11. Voltage Mode Control Loop with Loop Dynamic for Type III Compensation

The simple guidelines for positioning the poles and zeros and for calculating the

component values for Type III compensation are as follows: