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CC1050/TANDR 数据表(PDF) 13 Page - Texas Instruments |
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CC1050/TANDR 数据表(HTML) 13 Page - Texas Instruments |
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13 / 40 page  CC1050 SWRS044 Page 13 of 40 Figure 5. Configuration registers read operation Parameter Symbol Min Max Units Conditions PCLK, clock frequency FCLOCK - 10 MHz PCLK low pulse duration TCL,min 50 ns The minimum time PCLK must be low. PCLK high pulse duration TCH,min 50 ns The minimum time PCLK must be high. PALE setup time TSA 10 - ns The minimum time PALE must be low before negative edge of PCLK. PALE hold time THA 10 - ns The minimum time PALE must be held low after the positive edge of PCLK. PDATA setup time TSD 10 - ns The minimum time data on PDATA must be ready before the negative edge of PCLK. PDATA hold time THD 10 - ns The minimum time data must be held at PDATA, after the negative edge of PCLK. Rise time Trise 100 ns The maximum rise time for PCLK and PALE Fall time Tfall 100 ns The maximum fall time for PCLK and PALE Note: The set-up- and hold-times refer to 50% of VDD. Table 2. Serial interface, timing specification PCLK Address Read mode 65 4 3 21 0 R 7 6 5 4 3 2 1 0 Data byte PALE PDATA |
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