WM8150

Production Data

w

PD Rev 4.1 February 2005

12

MCLK

VSMP

VS

R

R

R

R

Figure 6 Reset Sample and Clamp Timing

For CIS type sensor signals, non-CDS processing is used. In this case, the video level is processed

with respect to the voltage on pin VRLC/VBIAS, generated internally or externally as described

mode; non-CDS processing is achieved by setting switch 2 in the lower position, CDS = 0.

OFFSET ADJUST AND PROGRAMMABLE GAIN

The output from the CDS block is a differential signal, which is added to the output of an 8-bit Offset

DAC to compensate for offsets and then amplified by an 8-bit PGA. The gain and offset can be set

for each of three colours by writing to control bits DACx[7:0] and PGAx[7:0] (where x can be R, G or

B).

In colour line-by-line mode the gain and offset coefficients that are applied to the PGA and offset

DAC can be multiplexed by control of the INTM[1:0] bits as shown in Table 1.

INTM[1:0]

DESCRIPTION

00

Red offset and gain registers are applied to offset DAC and PGA

(DACR[7:0] and PGAR[7:0])

01

Green offset and gain registers applied to offset DAC and PGA

(DACG[7:0] and PGAG[7:0])

10

Blue offset and gain registers applied to offset DAC and PGA

(DACB[7:0] and PGAB[7:0])

11

Reserved.

Table 1 Offset DAC and PGA Register Control

The gain characteristic of the WM8150 PGA is shown in Figure 7. Figure 8 shows the maximum

input voltage (at VINP) that can be gained up to match the ADC full-scale input range (2.5V).

0

1

2

3

4

5

6

7

8

9

0

64

128

192

256

GAIN REGISTER VALUE, PGA[7:0]

0

0.5

1

1.5

2

2.5

3

3.5

0

64

128

192

256

GAIN REGISTER VALUE, PGA[7:0]

Figure 7 PGA Gain Characteristic

Figure 8 Peak Input Voltage to Match ADC Full-scale Range