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WM8196SCDS 数据表(PDF) 9 Page - Wolfson Microelectronics plc |
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WM8196SCDS 数据表(HTML) 9 Page - Wolfson Microelectronics plc |
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9 / 32 page ![]() WM8196 Production Data w PD Rev 4.3 March 2007 9 OEB OP[7:0] t PZE Hi-Z t PEZ Hi-Z Figure 3 Output Data Enable Timing Test Conditions AVDD = DVDD1 = 5.0V, DVDD2 = 3.3V, AGND = DGND = 0V, TA = 25 °C, MCLK = 24MHz unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Output propagation delay tPD IOH = 1mA, IOL = 1mA 40 ns Output enable time tPZE 20 ns Output disable time tPEZ 15 ns MCLK RLC/ACYC PGA/OFFSET MUX OUTPUT t ACYCSU t ACYCH t ACYCSU t ACYCH Figure 4 Auto Cycle Timing Test Conditions AVDD = DVDD1 = 5.0V, DVDD2 = 3.3V, AGND = DGND = 0V, TA = 25 °C, MCLK = 24MHz unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Auto Cycle set-up time tACYCSU 6 ns Auto Cycle hold time tACYCH 3 ns |
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