WM8214SCDSSLASHR datasheet(30/36 Pages) WOLFSON

30 / 36 page

WM8214

Production Data

PD Rev 4.1 March 2007

The following table describes the function of each of the control bits shown in Table 7.

BIT

NAME(S)

DEFAULT

DESCRIPTION

Global Enable

0 = complete power down,

1 = fully active (individual blocks can be disabled using individual power down

bits – see setup register 5).

CDS

Select correlated double sampling mode:

0 = single ended mode,

1 = CDS mode.

MONO

Sampling mode select (see Table 5 for further details):

0 = other mode (2 or 3-channel)

1 = Monochrome (1-channel) mode. Input channel selected by CHAN[1:0]

TWOCHAN

Sampling mode select (see Table 5 for further details):

0 = other mode (1 or 3-channel)

1 = 2-channel mode. Inputs channels are Red and Green, Blue channel is

powered down.

5:4

PGAFS[1:0]

Offsets PGA output to optimise the ADC range for different polarity sensor

output signals. Zero differential PGA input signal gives:

0x = Zero output from the PGA (Output code=32767)

10 = Full-scale positive output (OP=65535) - use for negative going video.

NB, Set INVOP=1 if zero differential input should give a zero output

code with negative going video.

11 = Full-scale negative output (OP=0) - use for positive going video

MODE4LEG

This bit has no effect when LEGACY=0. Set this bit when operating in

LEGACY MODE4:

0 = other modes, 1 = LEGACY MODE4.

Setup

LEGACY

Makes the WM8214 timing compatible with the WM819x and WM815x AFE

families.

0 = Normal timing

1 = Enable LEGACY timing. Requires double rate MCLK and pixel rate VSMP

input. RSMP pin performs same function as RLC/ACYC pin on WM819x

devices.

WM8214SCDS/R 数据表(PDF) 30 Page - Wolfson Microelectronics plc

WM8214SCDS/R 数据表(HTML) 30 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

数据表下载