Production Data

WM8569

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PD Rev 4.0 June 2006

21

POWERDOWN MODES

The WM8569 has powerdown control bits allowing specific parts of the WM8569 to be powered off

when not being used. Control bit ADCPD powers off the ADC. The three stereo DACs each have a

separate powerdown control bit, DACPD[2:0] allowing individual stereo DACs to be powered off when

not in use. Setting ADCPD and DACPD[2:0] will powerdown everything except the references VMID

and REFADC. These may be powered down by setting PDWN. Setting PDWN will override all other

powerdown control bits. It is recommended that the ADC and DACs are powered down before setting

PDWN.

ZERO DETECT

The WM8569 has a zero detect circuit for each DAC channel that detects when 1024 consecutive

zero samples have been input. The MUTE pin output may be programmed to output the zero detect

signal which may then be used to control external muting circuits. A ‘1’ on MUTE indicates a zero

detect. The zero detect may also be used to automatically enable DAC mute by setting IZD.

SOFTWARE CONTROL INTERFACE OPERATION

The WM8569 is controlled using a 3-wire serial interface in software mode or pin

programmable in hardware mode.

The control mode is selected by the state of the MODE pin.

3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE

SDIN/DM is used for the program data, SCLK/IWL is used to clock in the program data and CSB/IDF

is used to latch the program data. SDIN/DM is sampled on the rising edge of SCLK/IWL. The 3-wire

interface protocol is shown in Figure 20.

Figure 20 3-Wire SPI Compatible Interface

Notes:

1.

B[15:9] are Control Address Bits

2.

B[8:0] are Control Data Bits

3.

CSB/IDF is edge sensitive – the data is latched on the rising edge of CSB/IDF.