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WM8580 数据表(PDF) 13 Page - Wolfson Microelectronics plc |
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WM8580 数据表(HTML) 13 Page - Wolfson Microelectronics plc |
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13 / 92 page  Production Data WM8580 w PD Rev 4.0 February 2007 13 DIGITAL AUDIO INTERFACE – SLAVE MODE Figure 3 Digital Audio Data Timing – Slave Mode Test Conditions AVDD, PVDD = 5V, DVDD = 3.3V, AGND = 0V, PGND,DGND = 0V, TA = +25 oC, Slave Mode, fs = 48kHz, MCLK and ADCMCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Audio Data Input Timing Information PAIFTX_BCLK/ PAIFRX_BCLK/SAIF_BCLK cycle time tBCY 50 ns PAIFTX_BCLK/ PAIFRX_BCLK/SAIF_BCLK pulse width high tBCH 20 ns PAIFTX_BCLK/ PAIFRX_BCLK/SAIF_BCLK pulse width low tBCL 20 ns PAIFTX_LRCLK/ PAIFRX_LRCLK/SAIF_BCLK set-up time to PAIFTX_BCLK/ PAIFRX_BCLK/SAIF_BCLK rising edge tLRSU 10 ns PAIFTX_LRCLK/ PAIFRX_LRCLK/ SAIF_LRCLK hold time from PAIFTX_BCLK/ PAIFRX_BCLK/SAIF_BCLK rising edge tLRH 10 ns DIN1/2/3/SAIF_DIN set-up time to PAIFRX_BCLK/ SAIF_BCLK rising edge tDS 10 ns DIN1/2/3/SAIF_DIN hold time from PAIFRX_BCLK/SAIF_BCLK rising edge tDH 10 ns DOUT/SAIF_DOUT propagation delay from PAIFTX_BCLK/SAIF_BCLK falling edge tDD 0 10 ns Table 5 Digital Audio Data Timing – Slave Mode |
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