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WM8590GEDS/V 数据表(PDF) 12 Page - Wolfson Microelectronics plc |
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WM8590GEDS/V 数据表(HTML) 12 Page - Wolfson Microelectronics plc |
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12 / 51 page ![]() WM8590 Production Data w PD Rev 4.0 January 2006 12 3-WIRE MPU INTERFACE TIMING Figure 6 SPI Compatible (3-wire) Control Interface Input Timing Test Conditions AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25 oC, fs = 48kHz, MCLK = 256fs unless otherwise stated PARAMETER SYMBOL MIN TYP MAX UNIT CL rising edge to CE rising edge tSCS 60 ns CL pulse cycle time tSCY 80 ns CL pulse width low tSCL 30 ns CL pulse width high tSCH 30 ns DI to CL set-up time tDSU 20 ns CL to DI hold time tDHO 20 ns CE falling edge to CL rising edge tCSC 20 ns CE pulse width high tCSH 20 ns CE rising to CL rising tCSS 20 ns Table 4 3-wire SPI Compatible Control Interface Input Timing Information |
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