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WM8706SEDS/R 数据表(PDF) 9 Page - Wolfson Microelectronics plc |
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WM8706SEDS/R 数据表(HTML) 9 Page - Wolfson Microelectronics plc |
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9 / 26 page  WM8706 Production Data w PD Rev 4.1 July 2005 9 MPU INTERFACE TIMING MLIIS MCDM1 MDDM0 t CSL t DHO t DSU t CSH t SCY t SCH t SCL t SCS LSB t CSS CSBIWO t CSSH t CSSU Figure 3 Program Register Input Timing - 3-Wire Serial Control Mode Test Conditions AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25 oC, fs = 48kHz, XTI = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Program Register Input Information MCDM1 rising edge to MLIIS rising edge tSCS 40 ns MCDM1 pulse cycle time tSCY 80 ns MCDM1 pulse width low tSCL 20 ns MCDM1 pulse width high tSCH 20 ns MDDM0 to MCDM1 set-up time tDSU 20 ns MCDM1 to MDDM0 hold time tDHO 20 ns MLIIS pulse width low tCSL 20 ns MLIIS pulse width high tCSH 20 ns MLIIS rising to SCLK rising tCSS 20 ns CSBIWO to MLIIS set-up time tCSSU 20 Ns MLIIS to CSBIWO hold time tCSSH 20 ns |
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