WM8718

Production Data

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PD Rev 4.3 November 2006

12

INTERNAL POWER ON RESET CIRCUIT

Figure 4 Internal Power On Reset Circuit Schematic

The WM8718 includes an internal Power On Reset Circuit which is used reset the digital logic into

a default state after power up.

Figure 4 shows a schematic of the internal POR circuit. The POR circuit is powered from AVDD.

The circuit monitors DVDD and VMID and asserts PORB low if DVDD or VMID are below the

minimum threshold Vpor_off.

On power up, the POR circuit requires AVDD to be present to operate. PORB is asserted low until

AVDD and DVDD and VMID are established. When AVDD, DVDD, and VMID have been

established, PORB is released high, all registers are in their default state and writes to the digital

interface may take place.

On power down, PORB is asserted low whenever DVDD or VMID drop below the minimum

threshold Vpor_off.

If AVDD is removed at any time, the internal Power On Reset circuit is powered down and PORB

will follow AVDD.

In most applications the time required for the device to release PORB high will be determined by

the charge time of the VMID node.

Figure 5 Typical Power Up Sequence Where DVDD is Powered Before AVDD