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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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WM8720SEDS/R 数据表(PDF) 6 Page - Wolfson Microelectronics plc |
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WM8720SEDS/R 数据表(HTML) 6 Page - Wolfson Microelectronics plc |
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6 / 17 page  WM8720 Production Data w PD Rev 4.0 February 2005 6 BCKIN DIN LRCIN t BCH t BCL t BL t LB t BCY t DS t DH Figure 1 Audio Data Input Timing Test Conditions AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25 oC, fs = 48kHz, SCKI = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Audio Data Input Timing Information BCKIN pulse cycle time tBCY 100 ns BCKIN pulse width high tBCH 40 ns BCKIN pulse width low tBCL 40 ns BCKIN rising edge to LRCIN edge tBL 20 ns LRCIN rising edge to BCKIN rising edge tLB 20 ns DIN setup time tDS 20 ns DIN hold time tDH 20 ns SCKI t SCKIL t SCKIH t SCKY Figure 2 System Clock Timing Requirements Test Conditions AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25 oC, fs = 48kHz, SCKI = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT System Clock Timing Information System clock pulse width high tSCKIH 10 ns System clock pulse width low tSCKIL 10 ns System clock cycle time tSCKY 27 ns |
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