WM8728

Production Data

w

PD Rev 4.2 April 2004

21

DE-EMPHASIS MODE

Setting the DEEMPH register bit puts the digital filters into de-emphasis mode:

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0010

DAC Control

1

DEEMPH

0

De-emphasis mode select:

0 : De-emphasis Off

1: De-emphasis On

Table 12 De-emphasis Control

POWERDOWN MODE

mode. All trace of the previous input samples is removed, and all control register settings are

cleared. When PWDN is cleared again the first 16 input samples will be ignored, as the FIR will

repeat it's power-on initialisation sequence.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0010

DAC Control

2

PWDN

0

Power Down Mode Select:

0 : Normal Mode

1: Power Down Mode

Table 13 Powerdown control

DIGITAL AUDIO INTERFACE CONTROL REGISTERS

The WM8728 has a fully featured digital audio interface that is a superset of that contained in the

WM8716. Interface format is selected via the IWL[2:0] register bits in register M2 and the I

register bit in M3.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0010

DAC Control

5:3

IWL[2:0]

000000

Interface format Select

0011

Interface Control

0

I

0

Interface format Select

Table 14 Interface Format Controls

IW2

I

IW1

IW0

AUDIO INTERFACE DESCRIPTION

(NOTE 1)

0

0

0

0

16 bit right justified mode

0

0

0

1

20 bit right justified mode

0

0

1

0

24 bit right justified mode

0

0

1

1

24 bit left justified mode

0

1

0

0

16 bit I

0

1

0

1

24 bit I

0

1

1

0

20 bit I

0

1

1

1

20 bit left justified mode

1

0

0

0

16 bit DSP mode

1

0

0

1

20 bit DSP mode

1

0

1

0

24 bit DSP mode

1

0

1

1

32 bit DSP mode

1

1

0

0

16 bit left justified mode

Table 15 Audio Data Input Format

Note:

In all modes, the data is signed 2's complement. The digital filters always input 24-bit data. If the

DAC is programmed to receive 16 or 20 bit data, the WM8728 pads the unused LSBs with

ZEROS. If the DAC is programmed into 32-bit mode, the 8 LSBs are treated as zero.