Production Data

WM8775

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PD Rev 4.1, June 2006

23

MASTER MODE ADCLRC FREQUENCY SELECT

In Master mode the WM8775 generates ADCLRC and BCLK. These clocks are derived from the

master clock. The ratio of MCLK to ADCLRC is set by ADCRATE.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R12(0Ch)

0001100

ADCLRC Frequency

Select

2:0

ADCRATE[2:0]

010

Master Mode MCLK:ADCLRC

ratio select:

010: 256fs

011: 384fs

100: 512fs

101: 768fs

ADC OVERSAMPLING RATE SELECT

For ADC operation at 96kHz it is recommended that the user set the ADCOSR bit. This changes the

ADC signal processing oversample rate to 64fs.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R12(0Ch)

0001100

ADC Oversampling Rate

3

ADCOSR

0

ADC oversampling rate select

0: 128x oversampling

1: 64x oversampling

POWERDOWN MODE AND ADC DISABLE

Setting the PDWN register bit immediately powers down the WM8775, including the references,

overriding all other powerdown control bits. All trace of the previous input samples is removed, but all

control register settings are preserved. When PDWN is cleared, the digital filters will be re-initialised.

It is recommended that the 4-channel input mux and buffer, and ADC are powered down before

setting PDWN.

The ADC may also be powered down by setting the ADCPD disable bit. Setting ADCPD will disable

the ADC and select a low power mode. The ADC digital filters will be reset and will reinitialise when

ADCPD is reset.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0

PDWN

0

Power Down Mode Select:

0 : Normal Mode

1: Power Down Mode

1

ADCPD

0

ADC Disable:

0 : Normal Mode

1: Power Down Mode

R13(0Dh)

0001101

Powerdown Control

6

AINPD

0

Analogue Input Disable:

0 : Normal Mode

1 : Power Down Mode