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WM8786GEDS/V 数据表(PDF) 18 Page - Wolfson Microelectronics plc |
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WM8786GEDS/V 数据表(HTML) 18 Page - Wolfson Microelectronics plc |
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18 / 24 page ![]() WM8786 Production Data w PD Rev 4.2 February 2007 18 In I 2S mode, the MSB is available on the second rising edge of BCLK following an LRCLK transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of the next. Figure 21 I 2S Justified Audio Interface (assuming n-bit word length) In DSP/PCM mode, the left channel MSB is available on the 2 nd rising edge of BCLK following a rising edge of LRC. Right channel data immediately follows left channel data. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of the right channel data and the next sample. In device master mode, the LRC output will resemble the frame pulse shown in Figure 22. In device slave mode, Figure 23 it is possible to use any length of frame pulse less than 1/fs, providing the falling edge of the frame pulse occurs greater than one BCLK period before the rising edge of the next frame pulse. Figure 22 DSP/PCM Mode Audio Interface (mode A, Master) Figure 23 DSP/PCM Mode Audio Interface (mode A, Slave) |
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