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WM8985GEFL/R 数据表(PDF) 91 Page - Wolfson Microelectronics plc

部件名 WM8985GEFL/R
功能描述  Multimedia CODEC With Class D Headphone and Line Out
PDF  118 Pages
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制造商  WOLFSON [Wolfson Microelectronics plc]
网页  http://www.wolfsonmicro.com
标志 WOLFSON - Wolfson Microelectronics plc

WM8985GEFL/R 数据表(HTML) 91 Page - Wolfson Microelectronics plc

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Pre-Production
WM8985
w
PP, Rev 3.5, January 2007
91
REGISTER BITS BY ADDRESS
Notes:
1. Default values of N/A indicate non-latched data bits (e.g. software reset or volume update bits).
2. Register bits marked as "Reserved" should not be changed from the default.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
0 (00h)
[8:0]
RESET
N/A
Software reset
Resetting the
Chip
8
0
Reserved. Initialise to 0
7
OUT4MIXEN
0
OUT4 mixer enable
0=disabled
1=enabled
Power
Management
6
OUT3MIXEN
0
OUT3 mixer enable
0=disabled
1=enabled
Power
Management
5
PLLEN
0
PLL enable
0=PLL off
1=PLL on
Master Clock
and Phase
Locked Loop
(PLL)
4
MICBEN
0
Microphone Bias Enable
0 = OFF (high impedance output)
1 = ON
Input Signal
Path
3
BIASEN
0
Analogue amplifier bias control
0=disabled
1=enabled
Power
Management
2
BUFIOEN
0
Unused input/output tie off buffer enable
0=disabled
1=enabled
Power
Management
1 (01h)
1:0
VMIDSEL[1:0]
00
Reference string impedance to VMID pin
00 = off (250kΩ VMID to AGND1)
01=75kΩ
10=300kΩ
11=5kΩ
Power
Management
8
ROUT1EN
0
ROUT1 output enable
0=disabled
1=enabled
Power
Management
7
LOUT1EN
0
LOUT1 output enable
0=disabled
1=enabled
Power
Management
6
SLEEP
0
0 = normal device operation
1 = residual current reduced in device standby
mode
Power
Management
5
BOOSTENR
0
Right channel Input BOOST enable
0 = Boost stage OFF
1 = Boost stage ON
Power
Management
4
BOOSTENL
0
Left channel Input BOOST enable
0 = Boost stage OFF
1 = Boost stage ON
Power
Management
3
INPPGAENR
0
Right channel input PGA enable
0 = disabled
1 = enabled
Power
Management
2 (02h)
2
INPPGAENL
0
Left channel input PGA enable
0 = disabled
1 = enabled
Power
Management



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