ATMEGA8515L-8AC datasheet(10/21 Pages) ATMEL

10 / 21 page

ATmega8515(L)

2512JS–AVR–10/06

Instruction Set Summary

Mnemonics

Operands

Description

Operation

Flags

#Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD

Rd, Rr

Add two Registers

← Rd + Rr

Z,C,N,V,H

ADC

Rd, Rr

Add with Carry two Registers

← Rd + Rr + C

Z,C,N,V,H

ADIW

Rdl,K

Add Immediate to Word

Rdh:Rdl

← Rdh:Rdl + K

Z,C,N,V,S

SUB

Rd, Rr

Subtract two Registers

← Rd - Rr

Z,C,N,V,H

SUBI

Rd, K

Subtract Constant from Register

← Rd - K

Z,C,N,V,H

SBC

Rd, Rr

Subtract with Carry two Registers

← Rd - Rr - C

Z,C,N,V,H

SBCI

Rd, K

Subtract with Carry Constant from Reg.

← Rd - K - C

Z,C,N,V,H

SBIW

Rdl,K

Subtract Immediate from Word

Rdh:Rdl

← Rdh:Rdl - K

Z,C,N,V,S

AND

Rd, Rr

Logical AND Registers

← Rd • Rr

Z,N,V

ANDI

Rd, K

Logical AND Register and Constant

← Rd • K

Z,N,V

Rd, Rr

Logical OR Registers

← Rd v Rr

Z,N,V

ORI

Rd, K

Logical OR Register and Constant

← Rd v K

Z,N,V

EOR

Rd, Rr

Exclusive OR Registers

← Rd ⊕ Rr

Z,N,V

COM

One’s Complement

← $FF − Rd

Z,C,N,V

NEG

Two’s Complement

← $00 − Rd

Z,C,N,V,H

SBR

Rd,K

Set Bit(s) in Register

← Rd v K

Z,N,V

CBR

Rd,K

Clear Bit(s) in Register

← Rd • ($FF - K)

Z,N,V

INC

Increment

← Rd + 1

Z,N,V

DEC

Decrement

← Rd − 1

Z,N,V

TST

Test for Zero or Minus

← Rd • Rd

Z,N,V

CLR

Clear Register

← Rd ⊕ Rd

Z,N,V

SER

Set Register

← $FF

None

MUL

Rd, Rr

Multiply Unsigned

R1:R0

← Rd x Rr

Z,C

MULS

Rd, Rr

Multiply Signed

R1:R0

← Rd x Rr

Z,C

MULSU

Rd, Rr

Multiply Signed with Unsigned

R1:R0

← Rd x Rr

Z,C

FMUL

Rd, Rr

Fractional Multiply Unsigned

R1:R0

← (Rd x Rr)

<< 1

Z,C

FMULS

Rd, Rr

Fractional Multiply Signed

R1:R0

← (Rd x Rr)

<< 1

Z,C

FMULSU

Rd, Rr

Fractional Multiply Signed with Unsigned

R1:R0

← (Rd x Rr)

<< 1

Z,C

BRANCH INSTRUCTIONS

RJMP

Relative Jump

← PC + k + 1

None

IJMP

Indirect Jump to (Z)

← Z

None

RCALL

Relative Subroutine Call

← PC + k + 1

None

ICALL

Indirect Call to (Z)

← ZNone

RET

Subroutine Return

← STACK

None

RETI

Interrupt Return

← STACK

CPSE

Rd,Rr

Compare, Skip if Equal

if (Rd = Rr) PC

← PC + 2 or 3

None

1/2/3

Rd,Rr

Compare

− Rr

Z, N,V,C,H

CPC

Rd,Rr

Compare with Carry

− Rr − C

Z, N,V,C,H

CPI

Rd,K

Compare Register with Immediate

− K

Z, N,V,C,H

SBRC

Rr, b

Skip if Bit in Register Cleared

if (Rr(b)=0) PC

← PC + 2 or 3

None

1/2/3

SBRS

Rr, b

Skip if Bit in Register is Set

if (Rr(b)=1) PC

← PC + 2 or 3

None

1/2/3

SBIC

P, b

Skip if Bit in I/O Register Cleared

if (P(b)=0) PC

← PC + 2 or 3

None

1/2/3

SBIS

P, b

Skip if Bit in I/O Register is Set

if (P(b)=1) PC

← PC + 2 or 3

None

1/2/3

BRBS

s, k

Branch if Status Flag Set

if (SREG(s) = 1) then PC

←PC+k + 1

None

1/2

BRBC

s, k

Branch if Status Flag Cleared

if (SREG(s) = 0) then PC

←PC+k + 1

None

1/2

BREQ

Branch if Equal

if (Z = 1) then PC

← PC + k + 1

None

1/2

BRNE

Branch if Not Equal

if (Z = 0) then PC

← PC + k + 1

None

1/2

BRCS

Branch if Carry Set

if (C = 1) then PC

← PC + k + 1

None

1/2

BRCC

Branch if Carry Cleared

if (C = 0) then PC

← PC + k + 1

None

1/2

BRSH

Branch if Same or Higher

if (C = 0) then PC

← PC + k + 1

None

1/2

BRLO

Branch if Lower

if (C = 1) then PC

← PC + k + 1

None

1/2

BRMI

Branch if Minus

if (N = 1) then PC

← PC + k + 1

None

1/2

BRPL

Branch if Plus

if (N = 0) then PC

← PC + k + 1

None

1/2

BRGE

Branch if Greater or Equal, Signed

if (N

⊕ V= 0) then PC ← PC + k + 1

None

1/2

BRLT

Branch if Less Than Zero, Signed

if (N

⊕ V= 1) then PC ← PC + k + 1

None

1/2

BRHS

Branch if Half Carry Flag Set

if (H = 1) then PC

← PC + k + 1

None

1/2

BRHC

Branch if Half Carry Flag Cleared

if (H = 0) then PC

← PC + k + 1

None

1/2

BRTS

Branch if T Flag Set

if (T = 1) then PC

← PC + k + 1

None

1/2

BRTC

Branch if T Flag Cleared

if (T = 0) then PC

← PC + k + 1

None

1/2

BRVS

Branch if Overflow Flag is Set

if (V = 1) then PC

← PC + k + 1

None

1/2

BRVC

Branch if Overflow Flag is Cleared

if (V = 0) then PC

← PC + k + 1

None

1/2

BRIE

Branch if Interrupt Enabled

if ( I = 1) then PC

← PC + k + 1

None

1/2

BRID

Branch if Interrupt Disabled

if ( I = 0) then PC

← PC + k + 1

None

1/2

ATMEGA8515L-8AC 数据表(PDF) 10 Page - ATMEL Corporation

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ATMEGA8515L-8AC 数据表(PDF) 10 Page - ATMEL Corporation

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