AD8367 datasheet(13/24 Pages) AD

13 / 24 page

AD8367

Rev. A | Page 13 of 24

RMS DETECTION

The AD8367 contains a square-law detector that senses

the output signal and compares it to a calibrated setpoint of

354 mV rms, which corresponds to a 1 V p-p sine wave. This

setpoint is internally set and cannot be modified to change the

AGC setpoint and the resulting VOUT level without using

additional external components. This is described in the

Modifying the AGC Setpoint section.

Any difference between the output and setpoint generates

a current that is integrated by an external capacitor, CAGC,

connected from the DETO pin to ground, to provide an AGC

control voltage. There is also an internal 5 pF capacitor on the

DETO pin.

The resulting voltage is used as an AGC bias. For this

application, the MODE pin is pulled low and the DETO pin is

tied to the GAIN pin. The output signal level is then regulated

to 354 mV rms. The AGC bias represents a calibrated rms

measure of the received signal strength (RSSI). Since in AGC

mode the output signal is forced to the 354 mV rms setpoint

(−9.02 dBV rms), Equation 2 can be recast to express the

strength of the received signal, VIN-RMS, in terms of the AGC

bias VDETO.

VIN − RMS (dBV rms) = 54.02 + 50 × VDETO

(4)

where −54.02 dBV rms = −45 dB − 9.02 dBV rms.

For small changes in input signal level, VDETO responds with a

characteristic single-pole time constant, τAGC, which is

proportional to CAGC.

τAGC (μs) = 10 × CAGC (nf)

(5)

where the internal 5 pF capacitor is lumped with the external

capacitor to give CAGC.

AD8367 数据表(PDF) 13 Page - Analog Devices