ADCMP551/ADCMP552/ADCMP553

Rev. 0 | Page 10 of 16

TIMING INFORMATION

50%

50%

50%

DIFFERENTIAL

INPUT VOLTAGE

LATCH ENABLE

Q OUTPUT

Q OUTPUT

LATCH ENABLE

Figure 17. System Timing Diagram

Figure 17 shows the compare and latch features of the ADCMP55x family. Table 4 describes the terms in the diagram.

Table 4. Timing Descriptions

Symbol

Timing

Description

Input to Output High Delay

Propagation delay measured from the time the input signal crosses the reference (± the

input offset voltage) to the 50% point of an output low-to-high transition

Input to Output Low Delay

Propagation delay measured from the time the input signal crosses the reference (± the

input offset voltage) to the 50% point of an output high-to-low transition

Latch Enable to Output High Delay

Propagation delay measured from the 50% point of the latch enable signal low-to-high

transition to the 50% point of an output low-to-high transition

Latch Enable to Output Low Delay

Propagation delay measured from the 50% point of the latch enable signal low-to-high

transition to the 50% point of an output high-to-low transition

Minimum Hold Time

Minimum time after the negative transition of the latch enable signal that the input signal

must remain unchanged to be acquired and held at the outputs

Minimum Latch Enable Pulse Width

Minimum time the latch enable signal must be high to acquire an input signal change

Minimum Setup Time

Minimum time before the negative transition of the latch enable signal that an input

signal change must be present to be acquired and held at the outputs

Output Rise Time

Amount of time required to transition from a low to a high output as measured at the

20% and 80% points

Output Fall Time

Amount of time required to transition from a high to a low output as measured at the

20% and 80% points

Voltage Overdrive

Difference between the differential input and reference input voltages