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ADCMP606 数据表(PDF) 7 Page - Analog Devices

部件名 ADCMP606
功能描述  Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply CML Comparators
PDF  16 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADCMP606 数据表(HTML) 7 Page - Analog Devices

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ADCMP606/ADCMP607
Rev. 0 | Page 7 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Q 1
VEE 2
VP 3
Q
6
VCCI/VCCO
5
VN
4
ADCMP606
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
TOP VIEW
(Not to Scale)
ADCMP607
VCCO 1
VCCI 2
VEE 3
9 VEE
8 LE/HYS
7 SDN
Figure 3. ADCMP606 Pin Configuration
Figure 4. ADCMP607 Pin Configuration
Table 5. ADCMP606 (SC70-6) Pin Function Descriptions
Pin No.
Mnemonic
Description
1
Q
Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, VP, is greater
than the analog voltage at the inverting input, VN.
2
VEE
Negative Supply Voltage.
3
VP
Noninverting Analog Input.
4
VN
Inverting Analog Input.
5
VCCI/VCCO
Input Section Supply/Output Section Supply. Shared pin.
6
Q
Inverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than
the analog voltage at the inverting input, VIN.
Table 6. ADCMP607 (LFCSP-12) Pin Function Descriptions
Pin No.
Mnemonic
Description
1
VCCO
Output Section Supply.
2
VCCI
Input Section Supply.
3
VEE
Negative Supply Voltage.
4
VP
Noninverting Analog Input.
5
VEE
Negative Supply Voltage.
6
VN
Inverting Analog Input.
7
SDN
Shutdown. Drive this pin low to shut down the device.
8
LE/HYS
Latch/Hysteresis Control. Bias with resistor or current for hysteresis adjustment; drive low to latch.
9
VEE
Negative Supply Voltage.
10
Q
Inverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than the
analog voltage at the inverting input, VN, if the comparator is in compare mode.
11
VEE
Negative Supply Voltage.
12
Q
Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, VP, is greater than
the analog voltage at the inverting input, VN, if the comparator is in compare mode.
Heat Sink
Paddle
VEE
The metallic back surface of the package is electrically connected to VEE. It can be left floating because
Pin 3, Pin 5, Pin 9, and Pin 11 provide adequate electrical connection. It can also be soldered to the
application board if improved thermal and/or mechanical stability is desired.



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