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AD8202YRMZ-R7 数据表(PDF) 12 Page - Analog Devices |
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AD8202YRMZ-R7 数据表(HTML) 12 Page - Analog Devices |
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12 / 20 page ![]() AD8202 Rev. D | Page 12 of 20 THEORY OF OPERATION The AD8202 consists of a preamp and buffer arranged as shown in Figure 40. Like-named resistors have equal values. The preamp uses a dynamic bridge (subtractor) circuit. Identical networks (within the shaded areas), consisting of RA, RB, RC, and RG, attenuate input signals applied to Pin 1 and Pin 8. When equal amplitude signals are asserted at Input 1 and Input 8, and the output of A1 is equal to the common potential (that is, 0), the two attenuators form a balanced-bridge network. When the bridge is balanced, the differential input voltage at A1, and thus its output, is 0. Any common-mode voltage applied to both inputs keeps the bridge balanced and the A1 output at 0. Because the resistor networks are carefully matched, the common-mode signal rejection approaches this ideal state. However, if the signals applied to the inputs differ, the result is a difference at the input to A1. A1 responds by adjusting its output to drive RB, by way of RG, to adjust the voltage at its inverting input until it matches the voltage at its noninverting input. By attenuating voltages at Pin 1 and Pin 8, the amplifier inputs are held within the power supply range, even if Pin 1 and Pin 8 input levels exceed the supply or fall below common (ground). The input network also attenuates normal (differential) mode voltages. RC and RG form an attenuator that scales A1 feedback, forcing large output signals to balance relatively small differen- tial inputs. The resistor ratios establish the preamp gain at 10. Because the differential input signal is attenuated and then amplified to yield an overall gain of 10, Amplifier A1 operates at a higher noise gain, multiplying deficiencies such as input offset voltage and noise with respect to Pin 1 and Pin 8. A1 A3 RCM RCM (TRIMMED) 100k Ω RA –IN RG RC RB RA RC RB RG +IN COM A2 RF RF AD8202 5 4 3 1 2 8 Figure 40. Simplified Schematic To minimize these errors while extending the common-mode range, a dedicated feedback loop is used to reduce the range of common-mode voltage applied to A1 for a given overall range at the inputs. By offsetting the voltage range applied to the com- pensator, the input common-mode range is also offset to include voltages more negative than the power supply. Amplifier A3 detects the common-mode signal applied to A1 and adjusts the voltage on the matched RCM resistors to reduce the common-mode voltage range at the A1 inputs. By adjusting the common voltage of these resistors, the common-mode input range is extended while, at the same time, the normal mode signal attenuation is reduced, leading to better performance referred to input. The output of the dynamic bridge taken from A1 is connected to Pin 3 by way of a 100 kΩ series resistor, provided for low- pass filtering and gain adjustment. The resistors in the input networks of the preamp and the buffer feedback resistors are ratio-trimmed for high accuracy. The output of the preamp drives a gain-of-2 buffer amplifier, A2, implemented with carefully matched feedback resistors (RF). The 2-stage system architecture of the AD8202 enables the user to incorporate a low-pass filter prior to the output buffer. By separating the gain into two stages, a full-scale, rail-to-rail signal from the preamp can be filtered at Pin 3, and a half-scale signal, resulting from filtering, can be restored to full scale by the output buffer amp. The source resistance seen by the inverting input of A2 is approximately 100 kΩ to minimize the effects of the input bias current of A2. However, this current is quite small, and errors resulting from applications that mismatch the resistance are correspondingly small. The A2 input bias current has a typical value of 40 nA, however, this can increase under certain conditions. For example, if the input signal to the A2 amplifier is VCC/2, the output attempts to go to VCC due to the gain of 2. However, the output saturates because the maximum specified voltage for correct operation is 200 mV below VCC. Under these conditions the total input bias current increases (see Figure 41 for more information). |
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