3

1937J–DFLSH–9/05

AT45DB021B

3.

Block Diagram

4.

Memory Array

To provide optimal flexibility, the memory array of the AT45DB021B is divided into three levels of

granularity comprised of sectors, blocks and pages. The Memory Architecture Diagram illus-

trates the breakdown of each level and details the number of pages per sector and block. All

program operations to the DataFlash occur on a page-by-page basis; however, the optional

erase operations can be performed at the block or page level.

Figure 4-1.

Memory Architecture Diagram

FLASH MEMORY ARRAY

PAGE (264 BYTES)

BUFFER 2 (264 BYTES)

BUFFER 1 (264 BYTES)

I/O INTERFACE

SCK

CS

RESET

VCC

GND

RDY/BUSY

WP

SO

SI

SECTOR 0a = 8 Pages

2112 bytes (2K + 64)

SECTOR 0b = 248 Pages

65,472 bytes (62K + 1984)

Block = 2112 bytes

(2K + 64)

8 Pages

SECTOR 0

Page = 264 bytes

(256 + 8)

PAGE 0

PAGE 1

PAGE 6

PAGE 7

PAGE 8

PAGE 9

PAGE 1022

PAGE 1023

PAGE 14

PAGE 15

PAGE 16

PAGE 17

PAGE 18

PAGE 1021

SECTOR ARCHITECTURE

BLOCK ARCHITECTURE

PAGE ARCHITECTURE

BLOCK 0

BLOCK 1

BLOCK 30

BLOCK 31

BLOCK 32

BLOCK 33

BLOCK 126

BLOCK 127

BLOCK 62

BLOCK 63

BLOCK 64

BLOCK 65

BLOCK 2

SECTOR 0c = 256 Pages

67,584 bytes (64K + 2K)

SECTOR 1 = 512 Pages

135,168 bytes (128K + 4K)