AT43USB325E-AC datasheet(78/109 Pages) ATMEL

78 / 109 page

3355C–USB–4/05

AT43USB325

The microcontroller should write into the FIFO only if this bit is cleared. After it has completed

writing the data, it should set this bit. This data can be of zero length.

Hardware clears this bit after it receives an ACK. If the interrupt is enabled and if the TX Com-

plete bit is set, clearing the TX Packet Ready bit by the hardware causes an interrupt to the

microcontroller.

•Bit 3 – STALL_SENT_ACK: Acknowledge Stall Sent Interrupt

Firmware sets this bit to clear STALL SENT, CSR bit 3. The 1 written in the CSRACK3 bit is not

actually stored and thus does not have to be cleared.

•Bit 2 – RX_SETUP_ACK: Acknowledge RX SETUP Interrupt

Firmware sets this bit to clear RX SETUP, CSR bit2. The 1 written in the CSRACK2 bit is not

actually stored and thus does not have to be cleared.

•Bit 1 – RX_OUT_PACKET_ACK: Acknowledge RX OUT PACKET Interrupt

Firmware sets this bit to clear RX OUT PACKET, CSR bit1. The 1 written in the CSRACK1 bit is

not actually stored and thus does not have to be cleared.

•Bit 0 – TX_COMPLETE_ACK: Acknowledge TX COMPLETE Interrupt

Firmware sets this bit to clear TX COMPLETE, CSR bit0. The 1 written in the CSRACK0 bit is

not actually stored and thus does not have to be cleared.

AT43USB325E-AC 数据表(PDF) 78 Page - ATMEL Corporation