21

3599F–DFLASH–09/06

AT26DF161

10.1.5

WEL Bit

The WEL bit indicates the current status of the internal Write Enable Latch. When the WEL bit is

in the logical “0” state, the device will not accept any program, erase, Protect Sector, Unprotect

Sector, or Write Status Register commands. The WEL bit defaults to the logical “0” state after a

device power-up or reset. In addition, the WEL bit will be reset to the logical “0” state automati-

cally under the following conditions:

• Write Disable operation completes successfully

• Write Status Register operation completes successfully or aborts

• Protect Sector operation completes successfully or aborts

• Unprotect Sector operation completes successfully or aborts

• Byte/Page Program operation completes successfully or aborts

• Block Erase operation completes successfully or aborts

• Chip Erase operation completes successfully or aborts

If the WEL bit is in the logical “1” state, it will not be reset to a logical “0” if an operation aborts

due to an incomplete or unrecognized opcode being clocked into the device before the CS pin is

deasserted. In order for the WEL bit to be reset when an operation aborts prematurely, the entire

opcode for a program, erase, Protect Sector, Unprotect Sector, or Write Status Register com-

mand must have been clocked into the device.

10.1.6

RDY/BSY Bit

The RDY/BSY bit is used to determine whether or not an internal operation, such as a program

or erase, is in progress. To poll the RDY/BSY bit to detect the completion of a program or erase

cycle, new Status Register data must be continually clocked out of the device until the state of

the RDY/BSY bit changes from a logical “1” to a logical “0”.

Figure 10-1. Read Status Register

10.2

Write Status Register

The Write Status Register command is used to modify the SPRL bit of the Status Register

and/or to perform a Global Protect or Global Unprotect operation. Before the Write Status Regis-

ter command can be issued, the Write Enable command must have been previously issued to

set the WEL bit in the Status Register to a logical “1”.

To issue the Write Status Register command, the CS pin must first be asserted and the opcode

of 01h must be clocked into the device followed by one byte of data. The one byte of data con-

sists of the SPRL bit value, a don't care bit, four data bits to denote whether a Global Protect or

SCK

CS

SI

SO

MSB

23

1

0

00000101

67

5

410 11

9

812

21 22

17

20

19

18

15 16

13 14

23 24

OPCODE

MSB

MSB

DDDDDD

D

D

D

D

MSB

DDDDD

D

D

D

STATUS REGISTER DATA

STATUS REGISTER DATA

HIGH-IMPEDANCE