AT89C5115-RATUM datasheet(85/113 Pages) ATMEL

85 / 113 page

AT89C5115

4128F–8051–05/06

The bits SCH0 to SCH2 in ADCON register are used for the analog input channel

selection.

Table 60. Selected Analog input

Voltage Conversion

When the ADCIN is equals to VAREF the ADC converts the signal to 3FFh (full scale). If

the input voltage equals VAGND, the ADC converts it to 000h. Input voltage between

VAREF and VAGND are a straight-line linear conversion. All other voltages will result in

3FFh if greater than VAREF and 000h if less than VAGND.

Note that ADCIN should not exceed VAREF absolute maximum range (See section

“AC-DC”).

Clock Selection

The ADC clock is the same as CPU.

The maximum clock frequency is defined in the DC parmeter for A/D converter. A pres-

caler is featured (ADCCLK) to generate the ADC clock from the oscillator frequency.

if PRS = 0 then FADC = Fperiph / 64

if PRS > 0 then FADC = Fperiph / 2 x PRS

Figure 40. A/D Converter Clock

ADC Standby Mode

When the ADC is not used, it is possible to set it in standby mode by clearing bit ADEN

in ADCON register. In this mode the power dissipation is reduced.

IT ADC management

An interrupt end-of-conversion will occurs when the bit ADEOC is activated and the bit

EADC is set. For re-arming the interrupt the bit ADEOC must be cleared by software.

SCH2

SCH1

SCH0

Selected Analog Input

000

AN0

001

AN1

010

AN2

011

AN3

100

AN4

101

AN5

110

AN6

111

AN7

Prescaler ADCLK

A/D

Converter

ADC Clock

CPU

CLOCK

CPU Core Clock Symbol

÷ 2

AT89C5115-RATUM 数据表(PDF) 85 Page - ATMEL Corporation

AT89C5115-RATUM 数据表(HTML) 85 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载