2

Functional Description

BL602/BL604 main functions described as follows：

SPI

RISC

CPU

FPU

MPU

NVIC

ROM

Cache

TCM

UART

Flash Control

DMA Channels

Crypto Engines

WiFi 802.11b/g/n

BLE 4.2

SDIO Slave

QSPI

SDIO

x4

I2C

PWM

IR

DAC

ADC

EINT

GPIO

x2

x5

GPIO

eFUSE

SYSRAM

GLB REG

PMU

RTC

Timer x2

RF

Bus

Figure 2.1: System Architecture

2.1 CPU

BL602/BL604 32-bit RISC CPU contains FPU (floating-point unit) for 32-bit single-precision arithmetic, three-stage

pipelined (IF, EXE, WB), compressed 16 and 32-bit instruction set, standard JTAG debugger port including 4 hardware-

BL602/604 Datasheet

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